Sains Malaysiana 37(3): 239-243 (2008)

 

Comparison Analysis on Scaling the Vertical and Lateral

NMOSFET in Nanometer Regime

(Analisis Perbandingan Penskalaan NMOSFET Menegak dan

Mendatar dalam Regim Nanometer)

 

 

Ismail Saad

School of Engineering & IT, Universiti Malaysia Sabah (UMS)

Locked Bag 2073, 88999 Kota Kinabalu

Sabah, Malaysia

 

Ismail Saad, Ima Sulaiman, Razali Ismail

Faculty of Electrical Engineering

Universiti Teknologi Malaysia (UTM)

81310 Skudai, Johor, Malaysia

 

 

Received:  12 June 2008 /Accepted:  27 November 2007

 

 

 

ABSTRACT

 

Conventional lateral and vertical n-channel MOS transistors with channel length in the range of 100nm to 50nm have been systematically investigated by means of device simulation. The comparison analysis includes critical parameters that govern device performance. Threshold voltage VT roll-off, leakage current Ioff, drain saturation current IDsat and sub-threshold swing S were analyze and compared between the device. Due to double gate (DG) structure over the side of silicon pillar a better electrostatics potential control of channel is obtained in vertical device shown by an analysis on VT roll-off. A two decade higher of Ioff in planar device is observed with Lg=50nm. A factor of three times larger IDsat is observed for vertical MOSFETs compared to planar device. The sub-threshold swing S remains almost the same when the Lg larger than 80 nm. It increased rapidly when the Lg is scaled down to 50 nm due to the short channel effect SCE. However, the vertical device has a steady increase whereas the planar device has suffered immediate enhance of SCE. The analysis results confirmed that vertical MOSFET with double-gate structure is a potential solution to overcome SCE when scaled the channel length to 50nm and beyond.  

 

Keywords: Vertical MOSFET;  DIBL; Double-gate; Surrounding-gate

 

 

ABSTRAK

 

Kajian terperinci berkenaan transistor MOS jenis-n secara menegak dan mendatar dengan kepanjangan saluran Lg dalam lingkungan 50nm ke 100nm telah dijalankan berdasarkan pensimulasian peranti. Analisis perbandingan meliputi parameter kritikal yang mengukur prestasi peranti. Penurunan voltan ambang VT, arus bocoran Ioff, arus tepu salir IDsat dan ayunan sub-ambang S telah dianalisis dan dibanding antara peranti. Disebabkan struktur dua get (DG) di sisi tiang silikon, kebolehupayaan elektrokstatik kawalan saluran yang baik dapat dilihat pada peranti tegak dengan menjalankan analisis prestasi kejatuhan voltan ambang (VT). Dua dekad lebih tinggi Ioff dapat diperhatikan pada peranti mendatar dengan Lg=50nm. Faktor tiga kali lebih besar IDsat diperhatikan pada MOSFET menegak berbanding peranti mendatar. Ayunan sub-ambang S adalah hampir sama apabila Lg besar dari 80nm. Ia menaik secara mendadak apabila Lg diskalakan ke 50nm disebabkan kesan saluran pendek (SCE). Peranti menegak mempunyai kenaikan yang agak sekata manakala peranti mendatar mengalami kenaikan mendadak SCE. Keputusan analisis ini membuktikan bahawa MOSFET menegak dengan struktur dua-get adalah penyelesaian berpotensi bagi mengatasi SCE apabila kepanjangan saluran diskalakan ke 50nm dan ke bawah.

 

Kata kunci: MOSFET tegak; DIBL; Dua-get;Get-keliling

 

 

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