Sains Malaysiana 38(5)(2009): 693–698

Optimisation of N-Channel Trench Power MOSFET

Using 2^k Factorial Design Method

(Pengoptimuman MOSFET Kuasa Parit Salur-N

Menggunakan Kaedah Reka Bentuk Pemfaktoran 2k)

Nur Syakimah Binti Ismail*

Pusat Pengajian Kejuruteraan Mikroelektronik

Blok A, Pusat Pengajian Jejawi 1

Universiti Malaysia Perlis, 02600 Jejawi, Perlis

Ibrahim Ahmad

Electronics & Communication Engineering Department

College of Engineering, Universiti Tenaga Nasional

Km 7, Jalan Kajang-Puchong, 43009 Kajang, Selangor.

Hafizah Husain

Jabatan Kejuruteraan Elektrik, Elektronik & Sistem

Fakulti Kejuruteraan, Universiti Kebangsaan Malaysia

43600 UKM Bangi, Selangor D.E., Malaysia

Received: 29 August 2008 / Accepted: 26 December 2008

ABSTRACT

The main objective of this research is to optimize the trench depth, trench width, epitaxial resistivity and epitaxial thickness in trench power MOSFET so as to obtain high breakdown voltage but low on-resistance. Optimisation of these parameters are based on 2k factorial design method for achieving specific on-resistance 0.1 mΩcm2 and blocking voltage higher than 30 V. ATHENA and ATLAS software from Silvaco Int. were used for fabrication simulation and device electrical characterisation. The results obtained were, the optimisation value for trench width was 1.25 μm, trench depth was 1.25 μm, epitaxial thickness was 4.75 μm and epitaxial resistivity was 0.32 Ωcm. The predictive value of breakdown voltage was 39.41 V and significant to factors trench depth, epitaxial thickness and epitaxial resistivity. The predictive value for on-resistance was 0.105 mΩcm2 with significant to factors trench depth, epitaxial thickness and epitaxial resistivity. In conclusion, 2k factorial design method is successfully utilised in optimizing n-channel trench power MOSFET.

Keywords: 2k Factorial design method; optimisation; trench power MOSFET

ABSTRAK

Tujuan utama kajian ini dijalankan adalah untuk mengoptimumkan kedalaman parit, kelebaran parit, keberintangan epitaksi dan ketebalan epitaksi dalam MOSFET kuasa parit bagi mendapatkan kejatuhan voltan tinggi manakala rintangan-buka rendah. Pengoptimuman kedalaman parit, kelebaran parit, keberintangan epitaksi dan ketebalan epitaksi dilakukan berdasarkan kaedah reka bentuk pemfaktoran 2k untuk mendapatkan rintangan-buka tertentu 0.1 mΩcm2 dan voltan penahanan lebih tinggi daripada 30 V. Simulator ATHENA dan ATLAS daripada Silvaco Int. telah digunakan untuk membuat simulasi fabrikasi dan pencirian elektrik bagi peranti. Keputusan yang diperoleh adalah, nilai pengoptimuman bagi kelebaran parit ialah 1.25 μm, kedalaman parit ialah 1.25 μm, ketebalan epitaksi ialah 4.75 μm dan keberintangan epitaksi ialah 0.32 Ωcm. Nilai jangkaan bagi kejatuhan voltan ialah 39.41 V dan signifikan terhadap faktor kedalaman parit, ketebalan epitaksi dan keberintangan epitaksi. Nilai jangkaan bagi rintangan-buka ialah 0.105 mΩcm2 dan signifikan terhadap faktor kedalaman parit, ketebalan epitaksi dan keberintangan epitaksi. Kesimpulannya, kaedah reka bentuk pemfaktoran 2k telah berjaya digunakan untuk mengoptimumkan salur-n transistor parit kuasa MOSFET.

Kata kunci: Kaedah reka bentuk pemfaktoran 2k; MOSFET kuasa parit; pengoptimuman

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*Corresponding author; email: syakimah@unimap.edu.my